The 2X1 multiplexer VHDL Code and Testbench

2X1 multiplexer

It is a combinational digital design which is used to select 1 out of the 2 available inputs. The block diagram of 2X1 mux is given below:

Copy the following VHDL module and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux2_1 is
port (A, B, S: in std_logic;
         Y : out std_logic
        );
end mux2_1;

architecture dataflow of mux2_1 is
begin
     Y <= ((not(S)) and A) or (S and B);
end dataflow;

Copy the following testbench for 2X1 mux and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_mux2_1 is
end tb_mux2_1;

architecture behavior of tb_mux2_1 is

component mux2_1 is
port (A, B, S: in std_logic;
         Y : out std_logic
         );
end component;

signal A: std_logic := '0';
signal B: std_logic := '0';
signal S: std_logic := '0';

signal D: std_logic;

begin

   uut : mux2_1 port map (
            A => A,
            B => B,
            S => S,
            Y => Y
        ); 

process
   begin      
        wait for 100 ns;
        -- apply stimulus here
        -- If A = 0 and B =1
        A <= '0';
        B<= '1';
        S <= ‘0’;
        wait for 50 ns;
        S <= ‘1’;
        wait for 50 ns;
        -- If A = 1 and B =0
        A <= '1';
        B<= '0';
        S <= ‘0’;
        wait for 50 ns;
        S <= ‘1’;
        wait for 50 ns;
        -- If A = 1 and B =1
        A <= '1';
        B<= '1';
        S <= ‘0’;
        wait for 50 ns;
        S <= ‘1’;
        wait for 50 ns;
        wait;
  end process;

end;

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