The 3X8 decoder VHDL Code and Testbench

3X8 Decoder

It is a combinational digital design used to decode binary inputs. The block diagram of 3X8 decoder is shown below:

       

VHDL code of 3X8 decoder:

This example demonstrates the use of dataflow modeling style which uses boolean expressions of design, i.e. output pins defined in terms of input pins, for writing VHDL code. The boolean expression of 3X8 decoder is represented in following image:

Copy the following VHDL module and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity decoder3_8 is

port (A, B, C: in std_logic;

         D : out std_logic_vector(7 downto 0)

        );

end decoder3_8;

architecture dataflow of decoder3_8 is

begin

     D(0) <= (not(A)) and (not(B)) and (not(C));

     D(1) <= (not(A)) and (not(B)) and C;

     D(2) <= (not(A)) and B and (not(C));

     D(3) <= (not(A)) and B and C;

     D(4) <= A and (not(B)) and (not(C));

     D(5) <= A and (not(B)) and C;

     D(6) <= A and B and (not(C));

     D(7) <= A and B and C;

end dataflow;

Copy the following testbench for 3X8 decoder and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_decoder3_8 is
end tb_decoder3_8;

architecture behavior of tb_decoder3_8 is

component decoder3_8 is
port (A, B, C: in std_logic;

         D : out std_logic_vector(7 downto 0)

         );
end component;

signal A: std_logic := '0';
signal B: std_logic := '0';
signal C: std_logic := '0';

signal D: std_logic_vector(7 downto 0);

begin

   uut : decoder3_8 port map (
            A => A,
            B => B, 

            C => C,
            D => D
        );  

process
   begin       
        wait for 100 ns;

        -- apply stimulus here
        A <= '0'; B<= '0'; C<= '0';
        wait for 50 ns;
        A <= '0'; B<= '0'; C<= '1';
        wait for 50 ns; 

        A <= '0'; B<= '1'; C<= '0';
        wait for 50 ns;  

        A <= '0'; B<= '1'; C<= '1';
        wait for 50 ns; 

        A <= '1'; B<= '0'; C<= '0';
        wait for 50 ns;  

        A <= '1'; B<= '0'; C<= '1';
        wait for 50 ns; 

        A <= '1'; B<= '1'; C<= '0';
        wait for 50 ns;  

        A <= '1'; B<= '1'; C<= '1';
        wait for 50 ns;

        wait;
  end process;

end;

Comment below your feedback or issues about this code!