4-bit Binary to Gray Code Converter VHDL code and Testbench

4-bit Binary to Gray Code Converter

The truth table and circuit diagram of 4-bit Binary to Gray Code Converter is as shown below:

 
Copy the following VHDL module and paste it in your Xilinx ISE project: 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;       

entity binary_gray is

Port ( B : in  STD_LOGIC_VECTOR (3 downto 0);

                      G : out  STD_LOGIC_VECTOR (3 downto 0));

end binary_gray;

architecture dataflow of binary_gray is

begin

G(3)<=B(3);

G(2)<=B(3) xor B(2);

G(1)<=B(2) xor B(1);

G(0)<=B(1) xor B(0);

end dataflow;

Copy the following Testbench for full adder and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;   

ENTITY b_gtb_vhd IS

END b_gtb_vhd;

ARCHITECTURE dataflow OF b_gtb_vhd IS

COMPONENT binary_gray

PORT(

B : IN std_logic_vector(3 downto 0);

G : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

SIGNAL B :  std_logic_vector(3 downto 0) := (others=>'0');

SIGNAL G :  std_logic_vector(3 downto 0);

BEGIN

uut: binary_gray PORT MAP(

B => B,

G => G

);

tb : PROCESS

BEGIN

wait for 100 ns;

b<="0000";

wait for 70 ns;

b<="0001";

wait for 70 ns;

b<="0010";

wait for 70 ns;

b<="0011";

wait for 70 ns;

b<="0100";

wait for 70 ns;

b<="0101";

wait for 70 ns;

b<="0110";

wait for 70 ns;

b<="0111";

wait for 70 ns;

b<="1000";

wait for 70 ns;

b<="1001";

wait for 70 ns;

b<="1010";

wait for 70 ns;

b<="1011";

wait for 70 ns;

b<="1100";

wait for 70 ns;

b<="1101";

wait for 70 ns;

b<="1110";

wait for 70 ns;

b<="1111";

wait for 70 ns;

wait;

END PROCESS;

END;