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Pull-up and Pull-down ratios of NMOS

Posted by Gurpreet Kaur

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Posted by Gurpreet Kaur

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The 3X8 decoder VHDL Code and Testbench

3X8 Decoder It is a combinational digital design used to decode binary inputs. The block diagram of 3X8 decoder is shown below: VHDL code of 3X8 decoder: This example demonstrates the use of dataflow modeling style which uses boolean expressions of design, i.e. output pins defined in terms of input pins, for writing VHDL code. The boolean expression of 3X8 decoder is represented in following image: Copy the following VHDL module and paste it in your Xilinx ISE project: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity decoder3_8 is port (A, B, C: in std_logic; D : out std_logic_vector(7 downto 0) ); end decoder3_8; architecture dataflow of decoder3_8 is begin D(0) <= (not(A)) and (not(B)) and (not(C)); D(1) <= (not(A)) and (not(B)) and C; D(2) <= (not(A)) and B and (not(C)); D(3) <= (not(A)) and B and C; D(4) <= A and (not(B)) and (not(C));

The 2X1 multiplexer VHDL Code and Testbench

2X1 multiplexer It is a combinational digital design which is used to select 1 out of the 2 available inputs. The block diagram of 2X1 mux is given below: Copy the following VHDL module and paste it in your Xilinx ISE project: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mux2_1 is port (A, B, S: in std_logic; Y : out std_logic ); end mux2_1; architecture dataflow of mux2_1 is begin Y <= ((not(S)) and A) or (S and B); end dataflow; Copy the following testbench for 2X1 mux and paste it in your Xilinx ISE project: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_mux2_1 is end tb_mux2_1; architecture behavior of tb_mux2_1 is component mux2_1 is port (A, B, S: in std_logic; Y : out std_logic ); end component; signal A: std_logic := '0'; signal B: std_logic := '0'; signal S: std_logic := '0'; signal D: std_logic; begin

Pull-up and Pull-down ratios of NMOS

Pull-up and Pull-down ratio: It is defined as the ratio between the resistance offered by pull-up transistor, Rp.u. (depletion mode NMOS) and pull-down transistor, Rp.d. (Enhancement mode transistor) i.e. Rp.u./Rp.d. To determine Rp.u./Rp.d. of NMOS inverter driven by another NMOS inverter The basic arrangement of NMOS inverter driven by another NMOS inverter is shown in figure below: Here, Vout = Vin and set Vinv = 0.5VDD. At this point, both the NMOS inverters are in saturation region From the MOS Device design equations, we know that, the drain-source current (Ids) under saturation region is given as, But, for depletion mode transistor (Normally-ON pull-up transistor), Vgs = 0, therefore, Similarly, for enhancement mode transistor (pull-down transistor), Vgs = Vinv, therefore, Where, Wpu = width of pull-up transistor Lpu = length of pull-up transistor Wpd = width of pull-down transistor Lpd = length of pull-down transistor Since,

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Pull-up and Pull-down ratios of NMOS

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