The Full adder VHDL code and Testbench

Full adder

It is a combinational digital design which takes three 1-bit binary inputs and adds them to give sum and carry.

Copy the following VHDL module and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fulladder is
port (A, B, C: in std_logic;
        Sum, Carry : out std_logic
        );
end fulladder;

architecture dataflow of fulladder is
begin
     Sum <= A xor B xor C;
     Carry <= (A and B) or (B and C) or (A and C);
end dataflow;

Copy the following testbench for full adder and paste it in your Xilinx ISE project:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_fulladder is
end tb_fulladder;

architecture behavior of tb_fulladder is

component fulladder is
port (A, B, C: in std_logic;
         Sum, Carry : out std_logic
         );
end component;

signal A: std_logic := '0';
signal B: std_logic := '0';
signal C: std_logic := '0';

signal D: std_logic;

begin

   uut : fulladder port map (
            A => A,
            B => B,
            C => C,
            Sum => Sum,
            Carry => Carry
        ); 

process
   begin      
        wait for 100 ns;
        -- apply stimulus here
        A <= '0'; B<= '0'; C<= '0';
        wait for 50 ns;
        A <= '0'; B<= '0'; C<= '1';
        wait for 50 ns;
        A <= '0'; B<= '1'; C<= '0';
        wait for 50 ns;
        A <= '0'; B<= '1'; C<= '1';
        wait for 50 ns;
        A <= '1'; B<= '0'; C<= '0';
        wait for 50 ns;
        A <= '1'; B<= '0'; C<= '1';
        wait for 50 ns;
        A <= '1'; B<= '1'; C<= '0';
        wait for 50 ns;
        A <= '1'; B<= '1'; C<= '1';
        wait for 50 ns;
        wait;
  end process;

end;